1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to split gate, flash memory devices.
2. Description of Related Art
U.S. Pat. No. 5,532,178 of Liaw for "Gate Process for NMOS ESD Protection Circuits" shows an undoped silicide gate, with flash memory, with no floating gates and no control gates, for a ESD device where an N implant is unwanted, e.g. in PMOS device areas. At col. 5 lines 49 et seq. Liaw states the following "The undoped polysilicon gates of the NMOS ESD circuit give the NMOS devices a higher breakdown voltage Vg that ensures that the ESD circuit will protect the product devices. The undoped polysilicon gate electrode. . .also allows the use of thinner gate oxides thereby increasing the speed of the product devices."
U.S. Pat. No. 4,698,787 of Mukherjee et al. for "Single transistor electrically programmable memory device and method"
U.S. Pat. No. 4,964,143 of Haskell for an EPROM element employing self-aligning process; U.S. Pat. No. 5,067,108 of Jenq for Single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate; U.S. Pat. No. 4,599,706 of Guterman; U.S. Pat. No. 4,462,089 of Miida et al.; and U.S. Pat. No. 4,274,012 of Simko all show Electrically Erasable Programmable Read Only Memory (EEPROM) devices.